Opened 5 years ago

Closed 5 years ago

#12225 closed defect (fixed)

arm fails to start upon invalid attempt to concatenate int and string

Reported by: pmezard Owned by: atagar
Priority: Medium Milestone:
Component: Core Tor/Nyx Version:
Severity: Keywords:
Cc: Actual Points:
Parent ID: Points:
Reviewer: Sponsor:


The stack trace is:

Traceback (most recent call last):
  File "./run_arm", line 49, in <module>
  File "./run_arm", line 18, in main
  File "/home/pmezard/dev/arm/arm/", line 94, in main
  File "/usr/lib/python2.6/curses/", line 43, in wrapper
    return func(stdscr, *args, **kwds)
  File "/home/pmezard/dev/arm/arm/", line 640, in start_arm
  File "/home/pmezard/dev/arm/arm/", line 436, in redraw
  File "/home/pmezard/dev/arm/arm/util/", line 428, in redraw
    self.draw(self.max_x, self.max_y)
  File "/home/pmezard/dev/arm/arm/", line 254, in draw
    for label in (self.vals.nickname, " - " + my_address, ":" + self.vals.or_port, dir_port_label):
TypeError: cannot concatenate 'str' and 'int' objects

A possible fix:

commit 57c20fed78a263930e6774f7de47747a1861728a
Author: Patrick Mezard <>
Date:   Sat Jun 7 23:20:06 2014 +0200

    Fix invalid or_port type formatting when making labels

diff --git a/arm/ b/arm/
index 0c7e669..94cf893 100644
--- a/arm/
+++ b/arm/
@@ -251,7 +251,7 @@ class HeaderPanel(panel.Panel, threading.Thread):
       dir_port_label = ", Dir Port: %s" % self.vals.dir_port if self.vals.dir_port != "0" else ""
-      for label in (self.vals.nickname, " - " + my_address, ":" + self.vals.or_port, dir_port_label):
+      for label in (self.vals.nickname, " - " + my_address, ":%d" % self.vals.or_port, dir_port_label):
         if x + len(label) <= left_width:
           self.addstr(1, x, label)
           x += len(label)

I suppose it comes from:

return [(addr, int(port)) for (addr, port) in proxy_addrs]

done when generating listeners lists in stem. But I understand nothing about the code.

Child Tickets

Change History (2)

comment:1 Changed 5 years ago by atagar

Thanks! Pushed...

Arm's git codebase is in the middle of a rewrite to better take advantage of Stem (about a third of our codebase was dedicated to wrapping TorCtl with functionality Stem provides out of the box). Hence I'd expect it to be pretty unstable.

comment:2 Changed 5 years ago by atagar

Resolution: fixed
Status: newclosed

Oops, forgot to resolve.

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